NAND-based flash memories are widely used as the solid-state memory storage due to their compactness, low power consumption, low cost, high data throughput and reliability. Solid state drive (SSD) devices commonly employ NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
An issue for SSDs is the reliability of the storage elements over the life of the SSD. Over time, relatively high gate voltages applied to the storage elements during program and erase (P/E) cycles in the SSD may cause cumulative permanent changes to the storage element characteristics. Charge may become trapped in the gate oxide of the storage elements through stress-induced leakage current (SILC). As the charge accumulates, the effect of programming or erasing a storage element becomes less reliable and the overall endurance of the storage element decreases. Additionally, an increasing number of P/E cycles experienced by a storage element decreases the storage element's data retention capacity, as high voltage stress causes charge to be lost from the storage element's floating gate, resulting in increased Bit Error Rate (BER) of the memory storage device.
Design capabilities of SSD's are driven by application use cases. Consumer applications are driven primarily by cost, requiring low cost devices that can have limited endurance and limited retention, as long as a lifespan of a few years is obtained for a single-user usage model in which the SSD is operated for only a few hours a day. In contrast, enterprise applications require high reliability, high endurance and long service life. Some enterprise applications also require high retention. However, the factors dictating retention and endurance are related, allowing for varying specifications to accommodate specific use cases. For example, a SSD may have a write endurance of 10,000 cycles/block. By making the specification for retention less stringent, write endurance can be extended. In transaction-oriented applications, where data retention of a few weeks is acceptable, block write endurance can be extended to more than 10,000 cycles/block.
Accordingly it is important to be able to accurately determine both write endurance and retention. Prior art models for determine retention capabilities of NAND-based flash memory chips are typically based on delta read calculations and the assumption that delta read is monotonic. However, with scaled NAND geometries, delta read is not monotonic. Delta read can be both positive and negative for a particular retention time. Accordingly, prior art models based on the assumption that delta read are based on an incorrect assumption. This can lead to incorrect estimation of retention values for a particular NAND Device.
Accordingly, what is needed in the art is a method and apparatus that will allow for accurately determining retention capabilities of NAND-Flash devices and SSD's and assuring that NAND-Flash devices and SSD's maintain the determined retention capabilities.